Part Number Hot Search : 
LV320MB 12F62 075784 BYW81HR KBC1100 NST18 FS8N60 SP563
Product Description
Full Text Search
 

To Download CY62256VNLL-70SNC Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 CY62256VN
256K (32K x 8) Static RAM
Features
* Temperature Ranges -- Commercial: 0C to 70C -- Industrial: -40C to 85C -- Automotive-A: -40C to 85C -- Automotive-E: -40C to 125C * Speed: 70 ns * Low voltage range: 2.7V-3.6V * Low active power and standby power * Easy memory expansion with CE and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected * CMOS for optimum speed/power * Available in standard Pb-free and non Pb-free 28-lead (300-mil) narrow SOIC, 28-lead TSOP-I and 28-lead Reverse TSOP-I packages
Functional Description[1]
The CY62256VN family is composed of two high-performance CMOS static RAM's organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tri-state drivers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.
Logic Block Diagram
INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A14 A13 A12 A11 A1 A0 ROW DECODER
I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5
32K x 8 Y ARRA
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-06512 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 3, 2006
[+] Feedback
CY62256VN
Product Portfolio
Power Dissipation VCC Range (V) Product CY62256VNLL CY62256VNLL CY62256VNLL CY62256VNLL Range Com'l Ind'l Automotive-A Automotive-E Min. 2.7 2.7 2.7 2.7 Typ.[2] 3.0 3.0 3.0 3.0 Max. 3.6 3.6 3.6 3.6 Operating, ICC (mA) Typ.[2] 11 11 11 11 Max. 30 30 30 30 Standby, ISB2 (A) Typ.[2] 0.1 0.1 0.1 0.1 Max. 5 10 10 130
Pin Configurations
Narrow SOIC Top View
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11
22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8
TSOP I Top View (not to scale)
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12
A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE
7 6 5 4 3 2 1 28 27 26 25 24 23 22
8 9 10 11 12 13 14 15 16 17 18 19 20 21
TSOP I Reverse Pinout Top View (not to scale)
A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0
Pin Definitions
Pin Number Type A0-A14. Address Inputs I/O0-I/O7. Data lines. Used as input or output lines depending on operation WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted CE. When LOW, selects the chip. When HIGH, deselects the chip OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins GND. Ground for the device Description 1-10, 21, 23-26 Input 11-13, 15-19 27 20 22 14 28 Input/Output Input/Control Input/Control Input/Control Ground
Power Supply VCC. Power supply for the device
Note: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25C, and tAA = 70 ns.
Document #: 001-06512 Rev. *A
Page 2 of 12
[+] Feedback
CY62256VN
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage to Ground Potential (Pin 28 to Pin 14) .......................................... -0.5V to + 4.6V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.5V to VCC + 0.5V DC Input Voltage[3] .................................-0.5V to VCC + 0.5V Output Current into Outputs (LOW) .............................20 mA Device Range Industrial CY62256VN Commercial Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Ambient Temperature (TA)[4] 0C to +70C -40C to +85C VCC 2.7V to 3.6V
Automotive-A -40C to +85C Automotive-E -40C to +125C
Electrical Characteristics Over the Operating Range
-70 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input Leakage Voltage Input Leakage Current GND < VIN < VCC Com'l/Ind'l/Auto-A Auto-E Output Leakage Current GND < VIN < VCC, Output Disabled VCC Operating Supply Current Automatic CE Power down Current TTL Inputs Automatic CE Power-down CurrentCMOS Inputs VCC = 3.6V, IOUT = 0 mA, f = fMAX = 1/tRC Com'l/Ind'l/Auto-A Auto-E All Ranges IOH = -1.0 mA IOL = 2.1 mA Test Conditions VCC = 2.7V VCC = 2.7V 2.2 -0.5 -1 -10 -1 -10 11 100 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +10 +1 +10 30 300 Typ.[2] Max. Unit V V V V A A A A mA A
VCC = 3.6V, CE > VIH, All Ranges VIN > VIH or VIN < VIL, f = fMAX VCC = 3.6V, CE > VCC - 0.3V Com'l VIN > VCC - 0.3V or VIN < Ind'l/Auto-A 0.3V, f = 0 Auto-E
ISB2
0.1
5 10 130
A
Notes: 3. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 4. TA is the "Instant-On" case temperature
Document #: 001-06512 Rev. *A
Page 3 of 12
[+] Feedback
CY62256VN
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V Max. 6 8 Unit pF pF
Thermal Resistance[5]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board SOIC 68.45 26.94 TSOPI 87.62 23.73 RTSOPI 87.62 23.73 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC 10% GND < 5 ns Equivalent to: THEVENIN EQUIVALENT Rth OUTPUT Vth ALL INPUT PULSES 90% 90% 10% < 5 ns
Parameter R1 R2 RTH VTH
Value 1100 1500 645 1.750
Units Ohms Ohms Ohms Volts
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC = 1.4V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Com'l Ind'l/Auto-A Auto-E 0 tRC Conditions[6] Min. 1.4 0.1 3 6 50 ns ns Typ.[2] Max. Unit V A
tCDR tR[5]
[6]
Chip Deselect to Data Retention Time Operation Recovery Time
Data Retention Waveform
DATA RETENTION MODE VCC 1.8V tCDR CE
Note: 5. Tested initially and after any design or process changes that may affect these parameters. 6. No input may exceed VCC + 0.3V.
VDR > 1.4V
1.8V tR
Document #: 001-06512 Rev. *A
Page 4 of 12
[+] Feedback
CY62256VN
Switching Characteristics Over the Operating Range[7]
CY62256VN-70 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[10, 11]
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[8] OE HIGH to High-Z CE LOW to Low-Z
[8, 9] [8]
Min. 70
Max.
Unit ns
70 10 70 35 5 25 10 25 0 70 70 60 60 0 0 50 30 0 25 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE HIGH to High-Z[8, 9] CE LOW to Power-up CE HIGH to Power-down Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[8, 9] WE HIGH to Low-Z[8]
Notes: 7. Test conditions assume signal transition time of 5 ns or less timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOL/IOH and 100-pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-06512 Rev. *A
Page 5 of 12
[+] Feedback
CY62256VN
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2[13, 14]
t RC
CE tACE OE tDOE t LZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT t PU 50%
t HZOE tHZCE DATA VALID t PD
HIGH IMPEDANCE
DATA OUT
ICC 50% ISB
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC ADDRESS
CE tAW WE tSA t PWE tHA
OE tSD DATA I/O NOTE 17 t HZOE
Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied.
tHD
DATAINVALID
Document #: 001-06512 Rev. *A
Page 6 of 12
[+] Feedback
CY62256VN
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAINVALID t HD tHA tSCE
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
tWC ADDRESS
CE tAW tSA WE tSD DATA I/O NOTE 17 t HZWE DATA INVALID tLZWE t HD t HA
Document #: 001-06512 Rev. *A
Page 7 of 12
[+] Feedback
CY62256VN
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.8 1.6 1.4 NORMALIZED ICC 1.2 1.0 0.8 0.6 0.4 0.2 2.4 2.8 1.6 1.8 2.0 3.2 3.6 TA= 25C 1.4 1.2 1.0 ISB2 A 0.8 0.6 0.4 0.2 0.0 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 2.5 NORMALIZED tAA 2.0 1.6
VCC = 3.0V
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE
VCC = 3.0V
STANDBY CURRENT vs. AMBIENT TEMPERATURE 3.0 2.5 2.0
3. 3V
NORMALIZED ICC
1.5 1.0 0.5 0.0 ISB
V
cc
-55
25
125
-0.5
-55
25
=
105
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT 14 vs. OUTPUT VOLTAGE 12 10 8 6 4 2 0 0.0 1.0 2.0 3.0
TA = 25C
NORMALIZED tAA
1.4 1.2 1.0 0.8 0.6
1.5 1.0 0.5 0.0 1.65 TA = 25C
2.1
2.6
3.1
3.6
-55
25
125
OUTPUT SINK CURRENT (mA)
SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT (mA)
AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE -14 -12 -10 -8 -6
TA = 25C
OUTPUT VOLTAGE (V)
-4 0 0.0 0.5 1.0 1.5 2 2.5
OUTPUT VOLTAGE (V)
Document #: 001-06512 Rev. *A
Page 8 of 12
[+] Feedback
CY62256VN
Typical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 DELTA tAA (ns) 25.0 T = 25C A VCC = 3V 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 0.50 1 10 20 30 NORMALIZED ICC NORMALIZED ICC vs. CYCLE TIME 1.25
VCC = 3.0V
1.00 TA = 25C VIN = 0.5V
0.75
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High-Z Data Out Data In High-Z Read Write Deselect, Output Disabled Mode Deselect/Power-down Active (ICC) Active (ICC) Active (ICC) Power Standby (ISB)
Ordering Information
Speed (ns) 70 Ordering Code CY62256VNLL-70SNC CY62256VNLL-70SNXC CY62256VNLL-70ZC CY62256VNLL-70ZXC CY62256VNLL-70SNXI CY62256VNLL-70ZI CY62256VNLL-70ZXI CY62256VNLL-70ZRI CY62256VNLL-70ZRXI CY62256VNLL-70ZXA CY62256VNLL-70SNXE CY62256VNLL-70ZXE CY62256VNLL-70ZRXE 51-85071 51-85092 51-85071 51-85074 51-85074 51-85071 51-85071 Package Diagram Package Type 28-lead (300-mil) Narrow SOIC (Pb-Free) 28-lead TSOP I 28-lead TSOP I (Pb-Free) 51-85092 28-lead (300-mil) Narrow SOIC (Pb-Free) 28-lead TSOP I 28-lead TSOP I (Pb-Free) 28-lead Reverse TSOP I 28-lead Reverse TSOP I (Pb-Free) 28-lead TSOP I (Pb-Free) 28-lead (300-mil) Narrow SOIC (Pb-Free) 28-lead TSOP I (Pb-Free) 28-lead Reverse TSOP I (Pb-Free) Automotive-A Automotive-E Industrial Operating Range Commercial
51-85092 28-lead (300-mil) Narrow SOIC
Please contact your local Cypress sales representative for availability of other parts
Document #: 001-06512 Rev. *A
Page 9 of 12
[+] Feedback
CY62256VN
Package Diagrams
28-lead (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
28-lead TSOP 1 (8 x 13.4 mm) (51-85071)
51-85071-*G
Document #: 001-06512 Rev. *A
Page 10 of 12
[+] Feedback
CY62256VN
Package Diagrams (continued)
28-lead Reverse TSOP 1 (8 x 13.4 mm) (51-85074)
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-06512 Rev. *A
Page 11 of 12
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY62256VN
Document History Page
Document Title: CY62256VN 256K (32K x 8) Static RAM Document Number: 001-06512 REV. ** *A ECN NO. Issue Date 426504 488954 See ECN See ECN Orig. of Change NXR NXR New Data Sheet Added Automotive product Updated ordering Information table Description of Change
Document #: 001-06512 Rev. *A
Page 12 of 12
[+] Feedback


▲Up To Search▲   

 
Price & Availability of CY62256VNLL-70SNC

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X